Two-level interrupt service routine

ABSTRACT

A processor provides two-level interrupt servicing. In one embodiment, the processor comprises a storage device and an interrupt handler. The storage device is configured to store an interrupt identifier corresponding to an interrupt request. The interrupt handler is configured to recognize the interrupt request, initiate a common interrupt service routine responsive to recognizing the interrupt request and subsequently initiate an interrupt service routine corresponding to the stored interrupt identifier.

FIELD

The present disclosure generally relates to interrupt handling routines,and particularly relates to two-level interrupt handling routines inprocessors.

BACKGROUND

Computing systems, e.g., servers, desktop computers, and mobile devicessuch as portable computers, mobile phones, personal digital assistantsand the like conventionally include one or more processors, volatile andnonvolatile memory, controllers, and peripheral devices such as akeyboard, keypad, mouse, display, earpiece, etc. The various componentsof a computing system are interconnected via one or more system and/orperipheral buses over which data, address and/or control information istransferred between peripheral devices and processor(s) included in thesystem.

When a peripheral device requires servicing, the device may activate aninterrupt signal. An interrupt causes the system processor totemporarily halt normal program flow in order to service the interruptrequest. Commonly, an interrupt controller prioritizes and processes thevarious interrupt signals generated by peripheral devices. As such, theinterrupt controller functions as an interface between peripheraldevices and the system processor. Thus, the system processor is notburdened with low-level tasks associated with managing, prioritizing andscheduling interrupt requests generated by various peripheral devices.Because the system processor does not initially interface directly withperipheral devices when servicing interrupt requests, the processor mustbe provided an address or other information for identifying an InterruptService Routine (ISR) corresponding to a peripheral device requestingservicing. An ISR services interrupts generated by a particularperipheral device. Commonly, multiple ISRs are maintained in memory,each associated with a different peripheral device.

In one conventional approach, an address associated with an ISR ispassed to a system processor via a system bus. Particularly, aninterrupt controller issues an interrupt request to the systemprocessor. At the appropriate time, the system processor acknowledgesthe request. Such initial interrupt request and acknowledgment signalingcommonly occurs over signal lines running directly between the interruptcontroller and the system processor. After acknowledging the interruptrequest, the system processor executes a common interrupt handlerroutine, often referred to as First-Level Interrupt Handler (FLIH)routine, for handling tasks common to all interrupts. For example, FLIHroutines may save the status of the interrupted instruction or routine,determine the action required to process a particular interrupt andschedule the execution of device-specific ISRs, commonly referred to asSecond-Level Interrupt Handler (SLIH) routines. SLIH routines processinterrupts associated with particular peripheral devices. The systemprocessor initiates an SLIH routine by accessing a memory locationassociated with the address information received from an interruptcontroller.

The interrupt controller provides ISR address information to the systemprocessor via the system bus. Transferring ISR address information viathe system bus delays the initiation of a particular SLIH routine by thesystem processor. Depending upon the particular activity occurringwithin a computing system, the delay associated with acquiring ISRaddress information via the system bus can be lengthy. For example, ifthe system processor is reading or writing large amounts of data frommemory or is servicing other peripheral devices, access to the systembus for purposes of acquiring address information can be significantlydelayed.

A second conventional approach eliminates the delay associated withtransferring ISR address information to a system processor via a systembus. Particularly, address information is passed directly to a systemprocessor from an interrupt controller via a dedicated bus. For example,ARM Holdings plc offers a Vectored Interrupt Controller (part numberPL192, document reference # ARM DDI 0273A) having a dedicated bus forpassing ISR address information from an interrupt controller directly toa system processor. As such, the system processor can initiatecorresponding SLIH routines more rapidly.

However, system processors do not conventionally store the ISR addressinformation locally within the processor for subsequent use. Instead,when a conventional processor receives ISR address information from aninterrupt controller over a dedicated bus, it immediately initiates acorresponding SLIH routine without first executing a common FLIHroutine. That is, the processor immediately jumps to a memory locationassociated with a particular SLIH routine without executing common FLIHcode. Thus, each SLIH routine must contain common first-level interrupthandling code which is duplicative, inefficient, increases thelikelihood of errors, and reduces code portability.

SUMMARY OF THE DISCLOSURE

According to the methods and apparatus taught herein, a processor thatprovides two-level interrupt servicing is presented. In one or moreembodiments, the processor comprises a storage device and an interrupthandler. The storage device is configured to store an interruptidentifier corresponding to an interrupt request. The interrupt handleris configured to recognize the interrupt request, initiate a commoninterrupt service routine responsive to recognizing the interruptrequest and subsequently initiate an interrupt service routinecorresponding to the stored interrupt identifier.

Thus, in one embodiment, a processor services an interrupt byrecognizing an interrupt request, saving an interrupt identifiercorresponding to the interrupt request, initiating a common interruptservice routine responsive to recognizing the interrupt request, andsubsequently initiating an interrupt service routine corresponding tothe saved interrupt identifier.

Corresponding to the above apparatuses and methods in an embodiment ofthe invention, a complementary computer program product is embodied in acomputer readable medium for servicing interrupts by a processorcomprises program instructions for recognizing an interrupt request,saving an interrupt identifier corresponding to the interrupt request,initiating a common interrupt service routine responsive to recognizingthe interrupt request, and subsequently initiating an interrupt serviceroutine corresponding to the saved interrupt identifier.

Of course, the present disclosure is not limited to the above features.Those skilled in the art will recognize additional features upon readingthe following detailed description, and upon viewing the accompanyingdrawings.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a block diagram illustrating an embodiment of a processorincluding an interrupt handler.

FIG. 2 is a logic flow diagram illustrating an embodiment of programlogic for implementing a two-level interrupt service routine by aninterrupt handler.

FIG. 3 is a logic flow diagram illustrating an embodiment of programlogic for loading a saved interrupt identifier into a program counter.

FIG. 4 is a logic flow diagram illustrating another embodiment ofprogram logic for loading a saved interrupt identifier into a programcounter.

FIG. 5 is a logic flow diagram illustrating another embodiment ofprogram logic for implementing a two-level interrupt service routine byan interrupt handler.

DETAILED DESCRIPTION

FIG. 1 illustrates an embodiment of a processor 10 including aninterrupt handler 12. The processor 10 executes a collection of machineinstructions that instruct the processor 10 to take certain actions,including interrupt handling. Particularly, the interrupt handler 12included in the processor 10 services interrupt requests received by theprocessor 10. Incident to acknowledging an interrupt request, theinterrupt handler 12 receives an interrupt identifier (IRQ_ID) from aninterrupt controller 14, i.e., an address or other informationassociated with a peripheral device (not shown) requesting servicing.The interrupt handler 12 saves the interrupt identifier in the processor10, e.g., by storing the interrupt identifier in one of severalprocessor registers 16 or in memory 18 included in the processor 10.Responsive to an interrupt request, the processor 10 either finishes orsuspends any instruction or part thereof that is currently executing.

When responding to an interrupt request, the interrupt handler 12executes a common Interrupt Service Routine (ISR), often referred to asFirst-Level Interrupt Handler (FLIH) routine, for handling tasks commonto all interrupts. For example, a common FLIH routine may include one ormore of disabling lower priority interrupts, enabling higher priorityinterrupts for servicing, identifying a cause of the interrupt request,saving information corresponding to a state of the processor 10 onto astack and scheduling execution of a device-specific ISR. After invokingthe FLIH routine, the interrupt handler 12 subsequently initiates adevice-specific ISR, commonly referred to as Second-Level InterruptHandler (SLIH) routine, for processing an interrupt request issued by aparticular peripheral device or devices. Because the interruptidentifier is saved in the processor 10, the interrupt handler 12 maybegin executing a common FLIH routine first and then subsequentlyexecute a SLIH routine that corresponds to the saved interruptidentifier, thus enabling code associated with common interrupt handlingtasks to be contained in a common FLIH routine.

In one example, the processor 10 and the interrupt controller 14communicate via a dedicated communication channel 20 that directly linksthe processor 10 and the controller 14. The communication channel 20includes a link by which the interrupt controller 14 issues prioritizedinterrupt requests to the processor 10 (IRQ_REQ). The communicationchannel 20 further includes a link used by the processor 10 toacknowledge interrupt requests (IRQ_ACK) to the interrupt controller 14.The communication channel 20 also includes a link or bus by which aninterrupt identifier (IRQ_ID) is transmitted to the processor 10 fromthe interrupt controller 14. Interrupt request and acknowledgementsignals as well as interrupt identifiers may be multiplexed over areduced number of signal lines. Regardless of how the processor 10receives an interrupt identifier, the interrupt handler 12 uses anacquired interrupt identifier to subsequently initiate a device-specificSLIH routine after a common FLIH routine has been invoked.

In operation, the processor 10 retrieves instructions and correspondingdata from external memory 22. The processor 10 executes the instructionsand stores results to the external memory 22. In a non-limiting example,the processor memory 18, e.g., a cache, stores address and datainformation retrieved from the external memory 22 via a bus interfaceunit 24. The processor 10 further includes one or more execution units26 for executing program instructions such as interrupt handling. Forexample, the execution units 26 may comprises one or more instructionunits, completion units, branch units, floating point units, integerunits, and load/store units.

The processor 10 also includes registers 16, such as general purpose andspecial purpose registers 28, 30 for storing contextual data, stackpointers, flags, etc. Stack pointers indicate a zone in the processormemory 18 used for saving contextual data in response to the processor10 switching context from one program currently being executed toanother program, e.g., a zone in the processor memory 18 used for savingcontextual data when the processor 10 temporarily halts a program toservice an interrupt request. The processor 10 further includes aprogram counter 32 (also known as an instruction sequencer, aninstruction pointer or a task register) for designating the address ofthe next instruction to be executed. The interrupt handler 12 includedin the processor 10 may comprise one or more digital processingcircuits, configured according to computer program instructionsimplemented in software (or firmware). Such circuits may be shared withother processing and control functions associated with the processor 10,e.g., by the execution units 26. Those skilled in the art willappreciate that the processor 10 may comprise a single microprocessor, amulti-core microprocessor, or multiple microprocessors embedded in thesame system where one or more of the microprocessors may be pipelinedand/or superscalar.

When a peripheral device (not shown) requires servicing, it issues aninterrupt request to the interrupt controller 14. The interruptcontroller 14 monitors peripheral devices for interrupt requests andprioritizes and processes various interrupt requests received fromperipheral devices. The interrupt controller 14 sends a prioritizedinterrupt request (IRQ_REQ) to the processor 10 to indicate that aperipheral device requests servicing. In addition, the interruptcontroller 14 provides to the processor 10 an interrupt identifier(IRQ_ID) associated with the peripheral device requesting interruptservicing. The interrupt handler 12 included in the processor 10services interrupt requests received from the interrupt controller 14.

FIG. 2 illustrates program logic for servicing interrupt requests by theinterrupt handler 12. Interrupt processing “begins” with the interrupthandler 12 recognizing the interrupt request (Step 100). In one example,the interrupt handler 12 recognizes an interrupt request in response tothe interrupt controller 14 issuing an interrupt request (IRQ_REQ) tothe processor 10. In turn, the interrupt handler 12 issues an interruptacknowledgment (IRQ_ACK) when the processor 10 is ready to service therequest. In response to the interrupt acknowledgement, the interruptcontroller 14 transmits to the processor 10 an interrupt identifier(IRQ_ID) associated with the peripheral device requesting service.

The interrupt handler 12 saves the interrupt identifier in the processor10 for later use (Step 102). For example, the interrupt identifier maybe stored in one of the general or special purpose registers 28, 30 orin the processor memory 18. If saved in one of the general or specialpurpose registers 28, 30, one register is temporarily allocated forstoring the device interrupt identifier. Alternatively, a dedicatedregister 34 may store the interrupt identifier. Regardless of thestorage medium, the saved interrupt identifier is available for lateruse by the interrupt handler 12 for initiating a SLIH routine tailoredto the peripheral device that requested servicing. Because the interruptidentifier is saved in the processor 10, the interrupt handler 12 is notrequired to immediately jump to the tailored SLIH routine when it beginsservicing an interrupt request. Instead, the interrupt handler 12 mayfirst initiate execution of a common FLIH routine before initiating thetailored SLIH routine (Step 104). As such, code associated with commoninterrupt handling tasks may be contained in a single FLIH routineinstead of in each SLIH routine supported by the processor 10, thusminimizing errors, increasing interrupt service performance, andimproving code portability.

After the common FLIH routine has been invoked, the interrupt handler 12subsequently initiates the tailored SLIH routine by causing theprocessor 10 to jump to a memory address at which the tailored SLIHroutine is maintained (Step 106). In one example, the saved interruptidentifier comprises an address at which the tailored SLIH routine ismaintained in the external memory 22 or in the processor memory 18. Assuch, the interrupt handler 12 loads the interrupt identifier into theprogram counter 32 as illustrated by Step 108 of FIG. 3, e.g., byissuing an instruction that loads the program counter 32 with theinterrupt identifier. In some cases, the interrupt identifier mayrequire address translation so that the program counter 32 is loadedwith address information of the proper form. Regardless, the processor10 then jumps to the memory address associated with the interruptidentifier loaded in the program counter 32 as illustrated by Step 110of FIG. 3.

In another example, the saved interrupt identifier comprises otherinformation uniquely identifying the peripheral device requestingservice. As such, the interrupt handler 12 uses the saved interruptidentifier to look-up in the processor memory 18 or the external memory22, e.g., in a lookup table, a memory address corresponding to theinterrupt identifier as illustrated by Step 112 of FIG. 4. The interrupthandler 12 then initiates the tailored SLIH routine by loading theprogram counter 32 with the acquired memory address as illustrated byStep 114 of FIG. 4. The processor 10 then jumps to the memory addressloaded in the program counter 32 as illustrated by Step 116 of FIG. 4.Regardless of the content of an interrupt identifier, the interrupthandler 12 may delete a stored interrupt identifier from the processor10 once the stored interrupt identifier has been used to initiate acorresponding SLIH routine.

FIG. 5 illustrates program logic for servicing subsequent interruptrequests received by the processor 10 while the interrupt handler 12 isservicing a prior interrupt request, e.g. a nested interrupt request.Processing “begins” with the interrupt handler 12 recognizing asubsequent interrupt request while the interrupt handler 12 is servicinga prior interrupt request (Step 200). As part of the interruptrequest/acknowledgment process, the processor 10 receives from theinterrupt controller 14 an interrupt identifier associated with theperipheral device subsequently requesting servicing. The interrupthandler 12 saves the interrupt identifier in the processor 10 for lateruse (Step 202). In a non-limiting example, the subsequent interruptidentifier is saved by overwriting the stored interrupt identifiercorresponding to the prior interrupt request with the interruptidentifier corresponding to the subsequent interrupt request.

The interrupt handler 12 first commences execution of a common FLIHroutine before initiating a SLIH routine tailored to the newly-savedinterrupt identifier (Step 204). In one embodiment, e.g., when thesubsequent interrupt request is of a higher priority than the priorinterrupt request, the interrupt handler 12 suspends the SLIH routineassociated with the prior interrupt request and initiates the commonFLIH routine. In another embodiment, e.g., when the subsequent interruptrequest is of the same or lower priority as the prior interrupt request,the interrupt handler 12 allows the SLIH routine associated with theprior interrupt request to complete execution before initiating thecommon FLIH routine.

Regardless, after the common FLIH routine has been invoked responsive tothe subsequent interrupt request, the interrupt handler 12 theninitiates the SLIH routine associated with the newly stored interruptidentifier by causing the processor 10 to jump to a memory address atwhich the tailored SLIH routine is maintained (Step 206). In oneexample, the newly-saved interrupt identifier comprises an address atwhich the tailored SLIH routine is maintained in the external memory 22or in the processor memory 18. In another example, the newly-savedinterrupt identifier comprises other information uniquely identifyingthe peripheral device requesting service. Regardless, the interrupthandler 12 uses the newly-saved interrupt identifier to initiate thecorresponding SLIH routine as previously described.

With the above range of variations and applications in mind, it shouldbe understood that the present disclosure is not limited by theforegoing description, nor is it limited by the accompanying drawings.Instead, the present disclosure is limited only by the following claimsand their legal equivalents.

1. A method of servicing interrupts by a processor, comprising:recognizing an interrupt request; saving an interrupt identifiercorresponding to the interrupt request; initiating a common interruptservice routine responsive to recognizing the interrupt request; andsubsequently initiating an interrupt service routine corresponding tothe saved interrupt identifier, wherein subsequently initiating theinterrupt service routine corresponding to the saved interruptidentifier comprises subsequently jumping to a memory address associatedwith the saved interrupt identifier, wherein subsequently jumping to thememory address associated with the saved interrupt identifier comprises:subsequently loading the memory address associated with the savedinterrupt identifier into a program counter of the processor; andjumping to the memory address loaded in the program counter.
 2. Themethod of claim 1, wherein saving the interrupt identifier comprisessaving the interrupt identifier in a register included in the processor.3. The method of claim 1, wherein initiating the common interruptservice routine comprises initiating at least one of schedulingexecution of the interrupt request, disabling lower priority interrupts,enabling higher priority interrupts for servicing, identifying a causeof the interrupt request, and saving information corresponding to astate of the processor responsive to recognizing the interrupt request.4. The method of claim 1, wherein subsequently loading the memoryaddress associated with the saved interrupt identifier into the programcounter comprises: subsequently using the saved interrupt identifier tolook-up the memory address; and loading the memory address into theprogram counter.
 5. The method of claim 1, wherein subsequently loadingthe memory address associated with the saved interrupt identifier intothe program counter comprises loading the saved interrupt identifierinto the program counter.
 6. The method of claim 1, further comprisingdeleting the saved interrupt identifier after the interrupt serviceroutine corresponding to the saved interrupt identifier has beeninitiated.
 7. The method of claim 1, further comprising: recognizing asubsequent interrupt request; saving an interrupt identifiercorresponding to the subsequent interrupt request; initiating the commoninterrupt service routine responsive to recognizing the subsequentinterrupt request; and initiating an interrupt service routinecorresponding to the subsequently saved interrupt identifier after thecommon interrupt service routine has been initiated responsive torecognizing the subsequent interrupt request.
 8. The method of claim 7,wherein initiating the common interrupt service routine responsive torecognizing the subsequent interrupt request comprises initiating thecommon interrupt service routine after the prior interrupt serviceroutine has completed.
 9. The method of claim 7, wherein saving thesubsequent interrupt identifier comprises overwriting the savedinterrupt identifier corresponding to the prior interrupt request withthe interrupt identifier corresponding to the subsequent interruptrequest.
 10. A processor, comprising: a storage device configured tostore an interrupt identifier corresponding to an interrupt request; andan interrupt handler configured to recognize the interrupt request,initiate a common interrupt service routine responsive to recognizingthe interrupt request and subsequently initiate an interrupt serviceroutine corresponding to the stored interrupt identifier, wherein theinterrupt handler is configured to subsequently jump to the memoryaddress associated with the saved interrupt identifier by subsequentlyloading the memory address associated with the saved interruptidentifier into a program counter of the processor and jumping to thememory address loaded in the program counter.
 11. The processor of claim10, wherein the storage device comprises a register included in theprocessor.
 12. The processor of claim 10, wherein the interrupt handleris configured to initiate the common interrupt service routine byinitiating at least one of scheduling execution of the interruptrequest, disabling lower priority interrupts, enabling higher priorityinterrupts for servicing, identifying a cause of the interrupt request,and saving information corresponding to a state of the processorresponsive to recognizing the interrupt request.
 13. The processor ofclaim 10, wherein the interrupt handler is configured to subsequentlyinitiate the interrupt service routine corresponding to the storedinterrupt identifier by subsequently jumping to a memory addressassociated with the stored interrupt identifier.
 14. The processor ofclaim 10, wherein the interrupt handler is configured to subsequentlyload the memory address associated with the saved interrupt identifierinto the program counter by subsequently using the saved interruptidentifier to look-up the memory address and loading the memory addressinto the program counter.
 15. The processor of claim 10, wherein theinterrupt handler is configured to subsequently load the memory addressassociated with the saved interrupt identifier into the program counterby loading the saved interrupt identifier into the program counter. 16.The processor of claim 10, wherein the interrupt handler is furtherconfigured to delete the stored interrupt identifier after the interruptservice routine corresponding to the stored interrupt identifier hasbeen initiated.
 17. The processor of claim 10, wherein the storagedevice is farther configured to store an interrupt identifiercorresponding to a subsequent interrupt request and the interrupthandler is further configured to recognize the subsequent interruptrequest, initiate the common interrupt service routine responsive torecognizing the subsequent interrupt request and initiate an interruptservice routine corresponding to the subsequently saved interruptidentifier after the common interrupt service routine has been initiatedresponsive to recognizing the subsequent interrupt request.
 18. Theprocessor of claim 17, wherein the interrupt handler is configured toinitiate the common interrupt service routine responsive to recognizingthe subsequent interrupt request by initiating the common interruptservice routine after the prior interrupt service routine has completed.19. The processor of claim 17, wherein the storage device is configuredto store the subsequent interrupt identifier by overwriting the storedinterrupt identifier corresponding to the prior interrupt request withthe interrupt identifier corresponding to the subsequent interruptrequest.
 20. A computer program product embodied in a computer readablemedium for servicing interrupts by a processor, comprising: programinstructions for recognizing an interrupt request; program instructionsfor saving an interrupt identifier corresponding to the interruptrequest; program instructions for initiating a common interrupt serviceroutine responsive to recognizing the interrupt request; and programinstructions for subsequently initiating an interrupt service routinecorresponding to the saved interrupt identifier, wherein the programinstructions for subsequently initiating the interrupt service routinecorresponding to the saved interrupt identifier comprise programinstructions for subsequently jumping to a memory address associatedwith the saved interrupt identifier, wherein the program instructionsfor subsequently jumping to the memory address associated with the savedinterrupt identifier comprise: program instructions for subsequentlyloading the memory address associated with the saved interruptidentifier into a program counter of the processor; and programinstructions for jumping to the memory address loaded in the programcounter.
 21. The computer program product of claim 20, wherein theprogram instructions for subsequently loading the memory addressassociated with the saved interrupt identifier into the program countercomprise: program instructions for subsequently using the savedinterrupt identifier to look-up the memory address; and programinstructions for loading the memory address into the program counter.22. The computer program product of claim 20, wherein the programinstructions for subsequently loading the memory address associated withthe saved interrupt identifier into the program counter comprise programinstructions for loading the saved interrupt identifier into the programcounter.
 23. The computer program product of claim 20, furthercomprising program instructions for deleting the saved interruptidentifier after the interrupt service routine corresponding to thesaved interrupt identifier has been initiated.
 24. The computer programproduct of claim 20, further comprising: program instructions forrecognizing a subsequent interrupt request; program instructions forsaving an interrupt identifier corresponding to the subsequent interruptrequest; program instructions for initiating the common interruptservice routine responsive to recognizing the subsequent interruptrequest; and program instructions for initiating an interrupt serviceroutine corresponding to the subsequently saved interrupt identifierafter the common interrupt service routine has been initiated responsiveto recognizing the subsequent interrupt request.